The field of the invention is that of integrated circuits, in particular fabricating circuits with design changes.
In the course of developing an integrated circuit, the designers make use of extensive computer models that predict the electrical performance of a circuit that has been synthesized, e.g. in a computer program that accepts as input the logic requirements of a system and generates a schematic that performs the functions specified.
Such programs are very sophisticated, but not infallible.
During the logic technology qualification cycle, one of the major hurdles needed to overcome is performance limitations that prevent the system specification from being realized. This becomes more critical with advanced technology.
Numerous process changes and model to hardware correlation are needed to assess the performance specification for the technology. The performance assessment is often made on final product chips with four to six levels of metal. The turn-around-time of this trial and error method to achieve final product performance data is significantly long due to extensive BEOL (Back End Of Line) wiring levels used in the product chip. As we incorporate more device types and move towards System On a Chip (SOC) early readout and correlation of product performance becomes critical. The parametric data does not always match the product performance.
Product chip data at final test are currently correlated back to the inline parametric data taken during the passage of the wafer through the fab. Parametric data is monitored to provide look ahead and indicate whether the hardware heading to product wafer test is healthy and to predict final chip yield. Parametric monitoring has been performed in this way for multiple generations of integrated circuits, providing standard checks on electrical parameters including the transistor characteristics.
However, the reference macro designs on which the parametric data is obtained cannot accommodate all the numerous design/process variables that reflect all transistors in the actual product chip environment. Often, the inevitable differences between the parametric transistor design vs. product transistor design can result in conflicting data. For example, it often happens that the parametric transistor results measured inline meet the design manual specification and yet the product chip performance results do not meet the specification set for the chip.
As performance requirements increase, the margin for error or manufacturing tolerance is reduced, so that a deviation in the performance of an individual device may be magnified by the circuit within which the devices is located. The result may be that the circuit does not meet its specification, even though the device does.
Due to the complex process of fabricating transistors in various environments, it is possible to have different physical shapes for transistors in different environments. It becomes increasingly difficult to maintain transistor shapes constant across the chip with each scaling technology generation. Systematic technology process solutions (across chip solutions) can only resolve this issue to a certain degree.
In particular, across chip line width variation may produce transistors with different amounts of drive in different parts of the chip. This may affect the time when a following device is turned on or off and thus change the circuit timing from its specification. In some cases, there may be logic errors when a signal arrives late or early.
In addition to the foregoing problems that do not depend on the time to pass through the fab significantly, there are other issues that explicitly deal with the time between identification of a problem and implementation of a solution. Often, a performance limiting feature is only identified on fully finished wafers.
In order to identify such problems, the chips often need to be delayered down to a lower level where a FIB (focused ion beam) probe technique is used to evaluate the actual transistor behavior in the questionable circuit. These standard techniques simply consume too many resources and have very long turn-around-time.
For example, the transit time of a wafer through a fab takes several months which the exact turn-around-around time varies depending on specific chip design for Back-End-of-Line build and fab loading, so that it takes a significant amount of time for a test batch of wafers to emerge from the fab so that they can be tested more rigorously than is possible for the in-process testing. Once a problem is identified (and a possible solution found) it then takes a period of months for wafers embodying the solution to make their way through the fab so that tests can be run to confirm that the proposed solution does or does not work.
There are several current methods for assessing performance of the product
1. Actual product performance at speed—This approach needs a final test, and possibly a packaged module. Further, if a problem is seen it can be difficult to correlate the problem with particular devices.
2. The use of test modes (in the testing program) to evaluate parts of the circuit—This approach needs both a final test and also additional circuits on the chip (Silicon area=cost) and design effort.
3. Test points within the design—This approach provides direct access to devices, but also needs access to the first metal (in order to locate the test points) and the design functions require significant bench work and design effort.
4. Chip delayer and Focus Ion Beam (FIB) cutting+wiring of devices within the chip—This approach also needs for the final level to be completed. In addition, we need to know which device is causing a problem. Further, since this is a labor-intensive process, there will be only a small sample size, so that the particular components examined may not be the immediate cause of the problem (even if they contribute to the problem in a large statistical sample). This approach often fails to identify a problem that can be fixed when there is an inconclusive test output.
5. Correlation of parametric data to product performance —This approach also needs test data from the completed chip. It is also not always successful in correlating the circuit problem with the parametric data.